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CY23FS08-04
FailSafeTM 1.8V Zero Delay Buffer
Features

Functional Description
The CY23FS08-04 is a FailSafe Zero Delay Buffer with two reference clock inputs and eight phase aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch free operation is achieved by using a DCXO that serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08-04 is that the DCXO is in fact, the primary clocking source, that is synchronized (phase aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO is chosen as an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. For more information, see Table 2 on page 3. The CY23FS08-04 has three split power supplies; one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except VDDC is connected to 1.8V. VDDC is the power supply pin for internal circuits and is connected to 3.3V.
Internal DCXO for continuous glitch free operation Zero input-output propagation delay Low output cycle-to-cycle jitter (<46 ps RMS) Low output-output skew (<200 ps) 3.84 MHz reference input Supports industry standard input crystals Up to 133 MHz (industrial) outputs Phase-locked loop (PLL) bypass mode Dual reference inputs 28-pin SSOP 1.8V output power supplies 3.3V core power supply Industrial temperature
Logic Block Diagram
XIN XOUT REFSEL DCXO
REF1 REF2 FBK FailsafeTM Block PLL
4 4
CLKA[1:4] CLKB[1:4]
Decoder FAIL# /SAFE S[4:1] 4
Cypress Semiconductor Corporation Document Number: 001-17042 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 20, 2007
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CY23FS08-04
Pinouts
Figure 1. Pin Diagram - 28 Pin SSOP
REF1 REF2 VSSB CLKB1 CLKB2 S2 S3 VDDB VSSB CLKB3 CLKB4 VDDB VDDC XIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
CY23FS08 - 04
28 27 26 25 24 23 22 21 20 19 18 17 16 15
REFSEL FBK VSSA CLKA1 CLKA2 S1 S4 VDDA VSSA CLKA3 CLKA4 VDDA FAIL#/SAFE XOUT
28-pin SSOP
Table 1. Pin Definition - 28 Pin SSOP Pin Number 1,2 4,5,10,11 25,24,19,18 27 23,6,7,22 14 15 16 13 8,12 3,9 17,21 20,26 28 Pin Name REF1,REF2 CLKB[1:4] CLKA[1:4] FBK S[1:4] XIN XOUT FAIL#/SAFE VDDC VDDB VSSB VDDA VSSA REFSEL 5V Tolerant. Reference clock inputs Description
[3].
Bank B Clock Outputs.[1] CLKB3 and CLKB4 are differential signals when terminated as shown in Figure 8 on page 6. CLKB3 is negtive output, CLKB4 is positive output. Bank A Clock Outputs.[1] No Connect, Internal Feedback. Frequency Select Pins.[2] Reference Crystal Input. Reference Crystal Output. Valid Reference Indicator. A high level indicates a valid reference input. 3.3V Power Supply for the Internal Circuitry. 1.8V Power Supply for Bank B Outputs. Ground. 1.8V Power Supply for Bank A Outputs. Ground. Reference Select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected.[3]
Notes 1. Weak pull downs on all outputs. 2. Weak pull ups on these inputs. 3. Weak pull downs on these inputs.
Document Number: 001-17042 Rev. **
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Table 2. Configuration Table S[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1xxx XTAL (MHz) Min 15.36 15.36 15.36 15.36 15.36 15.36 15.36 15.36 Max 16.384 16.384 16.384 16.384 16.384 16.384 16.384 16.384 REF(MHz) Min 3.84 3.84 3.84 3.84 3.84 3.84 3.84 3.84 Max 4.096 4.096 4.096 4.096 4.096 4.096 4.096 4.096 OUT/REF Ratio Xtal/REF Ratio CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 4 4 4 4 4 4 4 4 32 Off Off Off Off 8 8 1 Off 32 Off Off Off Off 8 8 1 Off 32 32 Off 16 Off 16 8 10 Off 32 32 Off 16 Off 16 8 10 Off 32 32 32 32 Off 32 16 20 Off 32 32 32 32 Off 32 16 20 Off 32 32 32 32 32 32 16 20 Off 32 32 32 32 32 32 16 20 Off
FailSafe Function
The CY23FS08-04 is targeted at clock distribution applications that can or currently require continued operation, if the main reference clock fail. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods for switching between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another. This often requires complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL that greatly simplifies the system design. The CY23FS08-04 PLL is driven by the crystal oscillator that is phase aligned to an external reference clock. It is aligned in a way that the output of the device is effectively phase aligned to reference via the external feedback loop. This is accomplished
by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of 100 ppm from its nominal frequency. In this mode, if the reference frequency fails (that is, stop or disappear), the DCXO maintains its last setting. Then a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS08-04 provides four select bits, S1 through S4 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared indicating the system that the selected reference is valid.
Figure 2. Fail#/safe timing for input reference failing catastrophically
Missing REF Detected Valid REF but not Phase Aligned Phase Aligned
REF Feedback(Internal) =CLKOUT * 1/32 FAIL#/SAFE
Keeping Frequency for all CLKOUTs Trying to align phase between REF and Feedback
tFSL
Figure 3. Fail#/safe Timing formula
tFSH
tFSL(max)
= tREF
+
25ns
t FSH(min) = tREF + 25ns
Document Number: 001-17042 Rev. **
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Table 3. FailSafe Timing Table Parameter tFSL tFSH Description Fail#/Safe Assert Delay Fail#/Safe Deassert Delay Conditions Measured at 80% to 20%, Load = 15 pF Measured at 80% to 20%, Load = 15 pF See Figure 3 Min Max See Figure 3 Unit ns ns
DCXO and capture range
Failsafe has DCXO for tracking to incoming reference clock. The CY23FS08-04 is configured its capture range of approx +/- 100ppm with using pullable crystal that specified in Table 7. Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range
Reference + 100 ppm Reference Reference - 100 ppm
Reference Off Frequency
Output + 100 ppm Output Output - 100 ppm
Fail#/Safe Volt
tFSH tFSL Time
Document Number: 001-17042 Rev. **
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Figure 5. FailSafe Reference Switching Behavior
Failsafe typical frequency settling time
Initial valid Ref1 = 20 MHz +100 ppm, then switching to REF2 = 20 MHz OUTPUT FREQUENCY DELTA (ppm)
150
100
50
0 0 0.45 1.3
SETTLING TIME (ms)
2.5
Figure 6. FailSafe Effective Loop Bandwidth (Min)
Document Number: 001-17042 Rev. **
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Figure 7. Sample Timing of Muxing Between Two Reference Clocks 180C Out of Phase and Resulting Output Phase Offset Typical Settling Time (105 MHz)
REF1
REF2
REFSEL 0 ms
0 d eg
-1 8 0 d e g
0 ms 1 .4 m s
Figure 8. Output Termination for Differential Output and Measurement Setup for Single-Ended Outputs
R UP RS CLKB3 D if f e r e n t ia l D R IV E R CLKB4 R DN D if f e r e n t ia l O u t p u t T e r m in a t io n N e t w o r k f o r C L K B 3 a n d C L K B 4 M e a s u r e m e n t p o in t f o r s in g le - e n d e d c lo c k s R DN RS TP R UP V D D (1 .8 V )
TP
Document Number: 001-17042 Rev. **
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Figure 9. Waveforms for Timing Parameters
D u ty C y c le - t D C V D D /2 V D D /2 t1 t2 S le w R a te - t (S R ) 80% 20% t S R (O ) O u tp u t-O u tp u t S k e w - t S K (O ) V D D /2 t S R (O ) 80% 20% 0V V DD V D D /2 V DD 0V
V D D /2 t S K (O ) P a rt to P a rt S k e w - t S K (P P ) FBK, P a rt 1 FBK, P a rt 2 V D D /2
V D D /2 t S K (P P )
S ta tic P h a s e O ffs e t - t ( ) REF V D D /2
FBK
V D D /2 t ( )
Document Number: 001-17042 Rev. **
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CY23FS08-04
Absolute Maximum Conditions
Parameter VDD VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Description Supply Voltage Relative to VSS Non-functional Industrial Grade Functional MIL-STD-883, Method 3015 Mil-Specification 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. 2000 36.17 100.6 V-0 1 Condition Min -0.5 -0.5 -65 -40 Max 4.6 VDD+0.5 +150 85 125 Unit V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
Table 4. Operating Conditions for FailSafe Industrial Temperature Devices Parameter VDDC VDDA, VDDB TA CL CIN CXIN TPU 3.3V Supply Voltage 1.8V Supply Voltage Range Ambient Operating Temperature, Industrial Output Load Capacitance Input Capacitance (Except XIN) Crystal Input Capacitance (All internal caps off) Power Up Time for all VDDs to Reach Minimum Specified Voltage (Power ramps are monotonic) 10 0.05 Description Min 3.135 1.70 -40 Max 3.465 1.90 85 15 7 13 500 Unit V V C pF pF pF ms
Table 5. Electrical Characteristics for FailSafe Industrial Temperature Devices Parameter VIL VIH IIL IIH IOL IOH IDD IDDQ Description Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current Output High Current Dynamic Current Quiescent Current Test Conditions CMOS Levels, 30% of VDD CMOS Levels, 70% of VDD VIN = VSS (100k pull up only) VIN = VDD (100k pull down only) VOL = 0.5V, VDD = 1.8V VOH = VDD - 0.5V, VDD = 1.8V VDDA, VDDB, and VDDC are all at the maximum values, IOUT = 0mA, output frequency = maximum All inputs are grounded, PLL and DCXO are in bypass mode, Reference input = 0 10 10 75 250 0.7xVDD 50 50 Min Typ Max 0.3xVDD Unit V V A A mA mA mA A
Document Number: 001-17042 Rev. **
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Table 6. Switching Characteristics for FailSafe Industrial Temperature Devices Parameter [5] fREF fOUT fXIN tDC tSR(I) tSR(O) tSK(O) tSK(IB) t()[4] tD()[4] tJ(CC) Description Reference Frequency Output Frequency DCXO Frequency Duty Cycle Input Slew Rate Output Slew Rate Output to Output Skew Intrabank Skew Static Phase Offset Dynamic Phase Offset Cycle-to-Cycle Jitter Measured at VDD/2 Measured on REF1 Input, 30% to 70% of VDD Measured from 20% to 80% of VDD = 1.8V, 15 pF Load All outputs equally loaded, measured at VDD/2 All outputs equally loaded, measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Load = 15 pF, fOUT 6.25 MHz Industrial Grade 15 pF Load Test Conditions Min 1.0 1.0 15 40 0.5 0.3 - - - - - - Table 7. Pullable Crystal Specifications Parameter CR load C0 / C1 ESR Crystal Load Capacitance C0 / C1 Ratio Equivalent Series Resistance Description Min Typ 16 240 50 Max Unit pF Typ - - - - - - 110 - - 150 200 18 Max 4.1 133 25 60 4.0 3.0 200 75 250 200 250 46 Unit MHz MHz MHz % V/ns V/ns ps ps ps ps ps psRMS
Notes 4. The t() reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Document Number: 001-17042 Rev. **
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Ordering Information
Part Number Pb-Free CY23FS08OXI-04 CY23FS08OXI-04T 28-pin SSOP 28-pin SSOP - Tape and Reel Industrial, -40C to 85C Industrial, -40C to 85C Package Type Product Flow
Package Drawing and Dimensions
Figure 10. 28-Pin (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Document Number: 001-17042 Rev. **
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Document History Page
Document Title: CY23FS08-04 FailSafeTM 1.8V Zero Delay Buffer Document Number: 001-17042 REV. ** ECN NO. 1493204 Issue Date See ECN Orig. of Change XHT/WWZ/ New data sheet AESA Description of Change
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-17042 Rev. **
Revised September 20, 2007
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PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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